• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The bus system has a bus and a plurality of line sections connected to the bus via respective drivers. The bus with line sections that are not needed can be interrupted at optional break points.
    公开号:US20010004748A1
    申请号:US09/737,060
    申请日:2000-12-14
    公开日:2001-06-21
    发明作者:Aaron Nygren
    申请人:Infineon Technologies AG；
    IPC主号:G06F13-4022
    专利说明:
    [0001] 1. Field of the Invention [0001]
    [0002] The present invention relates to a bus system having a bus routed to an output and having a multiplicity of line sections connected to the bus at connection points via a respective driver (drive element). [0002]
    [0003] In semiconductor memories, for example, line sections are routed from individual memory cell arrays to buses that are capable of transmitting a multiplicity of signals. Such buses may be tristate buses, for example, that is to say buses that are capable of assuming three states, namely “driven high”, “driven low,” and “not driven”. [0003]
    [0004] Upstream of the connection points to the bus, the individual line sections contain the drivers, which amplify the signals in the individual lines of the respective line sections and select the line section or the line which is currently able to connect to the bus. [0004]
    [0005] FIG. 3 is a schematic illustration of a prior art bus system of the generic type. That bus system has a bus [0005] 1 which is routed to an output (DOUT) and to which a respective line section 3 0 to 3 7 is connected at connection points 2. Each line section 3 0 to 3 7 contains a driver 4 which can be driven via a respective control connection 5 in order to select from the line sections 3 0 to 3 7 that line section which is to be connected to the bus 1, and in order to amplify the signal carried in the selected line section.
    [0006] The line sections [0006] 3 0 to 3 7 may each be one line or else may also be a plurality of lines, for example eight lines. If there are a plurality of lines in one line section 3 0 to 3 7, the driver 4 can additionally select one line from the selected line section and can connect this line to the bus 1.
    [0007] The more drivers there are connected to such a tristate bus [0007] 1, the lower the operating speed of the tristate bus 1 becomes. This can be attributed to the fact that each further driver adds more source and drain paths and additional circuitry, which increases the capacity of the bus system. A higher capacity results in a loss of operating speed, however.
    [0008] This loss of operating speed can be compensated for, within certain limits, by increasing the driver power. This is only possible up to a relatively small degree, however, since increased source and drain surfaces for the more powerful drivers likewise increase the capacity. Furthermore, it should be noted that, with an increasing number of drivers, the number of drive lines [0008] 5 for the enable signals (enable signals for the respective drivers 4) also increases, which likewise contributes to an increase in capacity.
    [0009] This means that the bus system shown in FIG. 3 operates with excellent behavior while the number of drivers [0009] 4 is relatively small. However, the operating response of the bus system is increasingly impaired the more drivers with line sections 3 0 to 3 7 and drive lines 5 for enable signals are connected to the bus 1. This is because the operating response of each driver 4 is influenced by the capacities of the other drivers 4. In other words, each individual driver 4 can also “see” the other drivers 4.
    [0010] With a small number of drivers [0010] 4, for example with four drivers 4, this influence from the other drivers is relatively small. However, if there are 24 drivers, for example, the influence of the other drivers on the currently selected driver cannot be disregarded, because the driver which is then currently selected is loaded with the capacities of all the other 23 drivers. In other words, the operating speed of the bus system is reduced not inconsiderably in such a case. SUMMARY OF THE INVENTION
    [0011] The object of the present invention is to provide a bus system which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and which is capable, depending on requirements, of operating with minimum capacity loading so that the operating speed of the bus system is thus not impaired, or is impaired only slightly. [0011]
    [0012] With the above and other objects in view there is provided, in accordance with the invention, a bus system, comprising: [0012]
    [0013] a bus connected to an output; [0013]
    [0014] a multiplicity of drivers connected to the bus at respective connection points; [0014]
    [0015] a multiplicity of line sections each connected to the bus via a respective driver; and [0015]
    [0016] the bus being formed with an optional break point between at least two of the connection points. [0016]
    [0017] In other words, the bus in the bus system according to the invention can, depending on requirements, readily be broken between two connection points, which means that all the drivers in the signal direction upstream of the break point no longer contribute to the capacity of the bus system. That is to say that, in the bus system according to the invention, all the drivers situated “before” the break point are disregarded, permitting a considerable reduction in capacity which, for its part, in turn considerably reduces the decrease in the operating speed of the bus system. [0017]
    [0018] Accordingly, an opportunity is provided, if required, of breaking the bus between at least two connection points between the bus and the line sections. That is to say that the bus can readily be broken between two connection points between the bus and the line sections in the bus system according to the invention. Hence, the output signals from all the drivers situated on the bus before the break point in the signal direction are disregarded during evaluation of the signals produced at the output DOUT. An optional break point can be created, for example, by designing the bus [0018] 1 (cf. FIG. 3 first) between two connection points 2 such that it can easily be broken between these two connection points. This can be done, for example, by the action of an appropriate laser beam, by etching or by another form of removal. In other words, the break point arranged as an option in the bus system according to the invention makes it possible to ensure that drivers which are not required have no concurrent effect in the formation of the output signal DOUT (cf. FIG. 3), in order for long term operation of the bus system to be ensured in this manner.
    [0019] In accordance with an added feature of the invention, the optional break point enables the bus to be broken if required. [0019]
    [0020] In accordance with an additional feature of the invention, there are formed a plurality of break points at regular intervals along the bus. [0020]
    [0021] In accordance with another feature of the invention, the bus is a tristate bus. [0021]
    [0022] In accordance with a further feature of the invention, each line section comprises a plurality of lines. [0022]
    [0023] In accordance with again an added feature of the invention, the bus is reduced to one line. [0023]
    [0024] In accordance with again an additional feature of the invention, the bus is formed of a plurality of individual lines each having respective break points at different locations along the bus. [0024]
    [0025] In accordance with again another feature of the invention, there are provided a plurality of buses each formed of a plurality of individual lines. Those buses then differ from one another with regard to the locations of the break points along the buses and the number of lines in the buses. [0025]
    [0026] In accordance with a concomitant feature of the invention, there is provided a programmable unit defining the break points with “break” and “connect” states. [0026]
    [0027] Other features which are considered as characteristic for the invention are set forth in the appended claims. [0027]
    [0028] Although the invention is illustrated and described herein as embodied in a bus system, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. [0028]
    [0029] The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. [0029] BRIEF DESCRIPTION OF THE DRAWINGS
    [0030] FIG. 1 is a schematic illustration of a first exemplary embodiment of the invention; [0030]
    [0031] FIG. 2 is a schematic illustration of a further exemplary embodiment of the invention; and [0031]
    [0032] FIG. 3 is a similar view of a prior art bus system. [0032] DESCRIPTION OF THE PREFERRED EMBODIMENTS
    [0033] Reference is had to the introductory text above describing the prior art bus system shown in FIG. 3. In the figures, the same reference symbols are used for equivalent components in each case. [0033]
    [0034] Referring now to the figures of the drawing showing the invention in detail and first, particularly, to FIG. 1 thereof, there is seen an illustrative embodiment in which, of the line sections [0034] 3 0 to 3 7, which in this case may each comprise eight lines, for example, the line sections 3 0 to 3 3 with their associated drivers 4 do not impair the bus 1 at its output DOUT in terms of capacity. This is so because the bus 1 is interrupted, i.e., broken, between the connection points 2 for the line sections 3 3 and 3 4. The break was chosen at this point because only the line sections 3 4 to 3 7 with their associated drivers 4 are required in the present case. In other words, the invention provides break points on the bus 1 at the places where disconnection of line sections which are not required can be expected.
    [0035] These break points can be designed to be such that they represent “desired break points” for the bus [0035] 1, at which the bus can be interrupted electrically with particular ease. By way of example, the configuration of the bus 1 at particular locations at which there are break points may be such that the bus can easily be melted by the action of a laser beam for this purpose. Of course, other breaking options for the bus 1 are also conceivable, however, such as breaking it by means of the local action of an etchant.
    [0036] It is particularly advantageous, however, if the break points are produced by programmable units [0036] 6 having the states “break” and “connect.” These programmable units 6 are also able to be connected to a control unit 7 which drives the programmable units 6 so that they selectively enter the desired state.
    [0037] With reference to FIG. 2, there is shown a further exemplary embodiment of the invention, in which potential break points are provided between the connection points [0037] 2 for the line sections 3 1 and 3 2, for the line sections 3 3 and 3 4 and for the line sections 3 5 and 3 6. Subject to the bus being used in an eDRAM, for example, the bus can in this case be interrupted at the specified break points. It is thus possible to connect to the output DOUT of the bus 1 only the line sections 3 6 and 3 7 or only the line sections 3 4 to 3 7 or only the line sections 3 2 to 3 7 with their associated drivers 4 by interrupting the bus at the specified break points. Of course, it is also possible for all the line sections 3 0 to 3 7 to remain connected to the output DOUT, however, if the bus is not interrupted at the break points.
    [0038] If the bus is interrupted between the connection points to the line sections [0038] 3 5 and 3 6 in the embodiment shown in FIG. 2, ground potential GND can be applied to each of the control lines 5 for the drivers 4 in the line sections 3 0 to 3 5, as shown in FIG. 2.
    [0039] The buses [0039] 1 can be reduced to one line. Similarly, it is also possible for a plurality of buses 1 each to comprise individual lines 8 in which the programmable units 6 are arranged as break points in various positions, as illustrated in a detail A in FIG. 2.
    [0040] The invention thus easily provides the option of connecting to a bus [0040] 1 only those line sections 3 0 to 3 7 which are actually needed. Burning away or disconnecting the other line sections ensures that there is a low-capacity bus system whose operating speed is impaired only as little as possible by the capacities of the remaining line sections and drivers 4.
    权利要求:
    Claims (9)
    [1" id="US-20010004748-A1-CLM-00001] 1. A bus system, comprising:
    a bus connected to an output;
    a multiplicity of drivers connected to said bus at respective connection points;
    a multiplicity of line sections each connected to said bus via a respective said driver; and
    said bus being formed with an optional break point between at least two of said connection points.
    [2" id="US-20010004748-A1-CLM-00002] 2. The bus system according to
    claim 1 , wherein said optional break point enables said bus to be broken if required.
    [3" id="US-20010004748-A1-CLM-00003] 3. The bus system according to
    claim 1 , wherein said break point is one of a plurality of break points formed at regular intervals along said bus.
    [4" id="US-20010004748-A1-CLM-00004] 4. The bus system according to
    claim 1 , wherein said bus is a tristate bus.
    [5" id="US-20010004748-A1-CLM-00005] 5. The bus system according to
    claim 1 , wherein each said line section comprises a plurality of lines.
    [6" id="US-20010004748-A1-CLM-00006] 6. The bus system according to
    claim 1 , wherein said bus is reduced to one line.
    [7" id="US-20010004748-A1-CLM-00007] 7. The bus system according to
    claim 1 , wherein said bus is formed of a plurality of individual lines each having respective break points at different locations along said bus.
    [8" id="US-20010004748-A1-CLM-00008] 8. The bus system according to
    claim 1 , wherein said bus is one of a plurality of buses each formed of a plurality of individual lines, and wherein said buses differ from one another with regard to locations of said break points along said buses and a number of lines in said buses.
    [9" id="US-20010004748-A1-CLM-00009] 9. The bus system according to
    claim 1 , which comprises a programmable unit defining said break points with states selected from the group of “break” and “connect”.
    类似技术:
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    同族专利:
    公开号 | 公开日
    JP2001236152A|2001-08-31|
    EP1115067A2|2001-07-11|
    EP1115067A3|2004-01-28|
    TW522696B|2003-03-01|
    KR20010062425A|2001-07-07|
    DE19960243A1|2001-07-05|
    US6715012B2|2004-03-30|
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    法律状态:
    2004-02-06| AS| Assignment|Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NYGREN, AARON;REEL/FRAME:014962/0962 Effective date: 20000110 |
    2004-03-11| STCF| Information on status: patent grant|Free format text: PATENTED CASE |
    2007-09-21| FPAY| Fee payment|Year of fee payment: 4 |
    2010-01-13| AS| Assignment|Owner name: QIMONDA AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:023828/0001 Effective date: 20060425 |
    2011-09-19| FPAY| Fee payment|Year of fee payment: 8 |
    2015-05-08| AS| Assignment|Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QIMONDA AG;REEL/FRAME:035623/0001 Effective date: 20141009 |
    2015-08-19| AS| Assignment|Owner name: POLARIS INNOVATIONS LIMITED, IRELAND Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:036396/0646 Effective date: 20150708 |
    2015-11-06| REMI| Maintenance fee reminder mailed|
    2016-01-08| FPAY| Fee payment|Year of fee payment: 12 |
    2016-01-08| SULP| Surcharge for late payment|Year of fee payment: 11 |
    优先权:
    申请号 | 申请日 | 专利标题
    DE19960243A|DE19960243A1|1999-12-14|1999-12-14|Bus system|
    DE19960243.3||1999-12-14||
    DE19960243||1999-12-14||
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